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CY7B9910 CY7B9920
Low Skew Clock Buffer
Features
* * * * * * * * * All outputs skew <100 ps typical (250 max.) 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50 terminated lines Low operating current 24-pin SOIC package Jitter: <200 ps peak to peak, <25 ps RMS Compatible with PentiumTM-based processors
Block Diagram Description
Phase Frequency Detector and Filter These two blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal. VCO The VCO accepts analog control inputs from the PLL filter block and generates a frequency. The operational range of the VCO is determined by the FS control pin.
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low-skew system clock distribution. These multiple-output clock drivers optimize the timing of high-performance computer systems. Eight individual drivers can each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews and full-swing logic levels (CY7B9910 TTL or CY7B9920 CMOS). The completely integrated PLL allows "zero delay" capability. External divide capability, combined with the internal PLL, allows distribution of a low-frequency clock that can be multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.
Test Mode
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910/CY7B9920 to operate as explained above. (For testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100 resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase-locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode.
Logic Block Diagram
TEST PHASE FREQ DET FS Voltage FILTER Controlled Oscillator Q0 Q1 Q2 Q3 Q4 Q5 Q6
7B9910-1
Pin Configuration
FB REF
SOIC Top View
REF VCCQ FS NC VCCQ VCCN Q0 Q1 GND Q2 Q3 VCCN
1 2 3 4 5 6 7 8 9 10 11 12 7B9910 7B9920 24 23 22 21 20 19 18 17 16 15 14 13
GND TEST NC GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB
Q7
7B9910-2
Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 November 1994 - Revised July 7, 1997
CY7B9910 CY7B9920
Pin Definitions
Signal Name REF FB FS[9,10,11] TEST Q[0..7] VCCN VCCQ GND I/O I I I I O PWR PWR PWR Description Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. PLL feedback input (typically connected to one of the eight outputs). Three-level frequency range select. Three-level select. See Test Mode section. Clock outputs. Power supply for output drivers. Power supply for internal circuitry. Ground. Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Output Current into Outputs (LOW) ............................. 64 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CY7B9910 Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only) Input LOW Voltage (REF and FB inputs only) Three-Level Input HIGH Voltage (Test, FS)[1] Three-Level Input MID Voltage (Test, FS)[1] Three-Level Input LOW Voltage (Test, FS)[1] Input HIGH Leakage Current (REF and FB inputs only) Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS) Input MID Current (Test, FS) Input LOW Current (Test, FS) Min. VCC Max. Min. VCC Max. Min. VCC Max. VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND -50 -500 200 50 -200 -50 Test Conditions VCC = Min., IOH = -16 mA VCC = Min., IOH =-40 mA VCC = Min., IOL = 46 mA VCC = Min., IOL = 46 mA 2.0 -0.5 VCC - 1V VCC/2 - 500 mV 0.0 VCC 0.8 VCC VCC/2 + 500 mV 1.0 10 -500 200 50 -200 VCC - 1.35 -0.5 VCC - 1V VCC/2 - 500 mV 0.0 0.45 0.45 VCC 1.35 VCC VCC/2 + 500 mV 1.0 10 V V V V V A A A A A Min. 2.4 VCC -0.75 V Max. CY7B9920 Min. Max. Unit V
2
CY7B9910 CY7B9920
Electrical Characteristics Over the Operating Range (continued)
CY7B9910 Parameter IOS ICCQ Description Output Short Circuit Current[2] Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair[3] Power Dissipation per Output Pair[4] Test Conditions VCC = Max., VOUT = GND (25C only) VCCN = VCCQ = Max., Com'l All Input Mil/Ind Selects Open VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX Min. Max. -250 85 90 14 CY7B9920 Min. Max. N/A 85 90 19 mA Unit mA mA
ICCN
PD
78
104[5]
mW
Capacitance[6]
Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 Unit pF
Notes: 1. These inputs are normally wired to V CC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 2. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit protected. 3. Total output current per output pair can be approximated by the following expression that includes device current plus load current: CY7B9910: ICCN = [(4 + 0.11F) + [((835 - 3F)/Z) + (.0022FC)]N] x 1.1 CY7B9920: ICCN = [(3.5+ .17F) + [((1160 - 2.8F)/Z) + (.0025FC)]N] x 1.1 Where F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 FC = F < C 4. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: CY7B9910: PD = [(22 + 0.61F) + [((1550 - 2.7F)/Z) + (.0125FC)]N] x 1.1 CY7B9920: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1 See note 3 for variable definition. 5. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency. 6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V R1 CL R1=130 R2=91 CL = 50 pF (CL = 30pF for -5 and - 2 devices) (Includes fixture and probe capacitance)
7B9910-3
3.0V 2.0V Vth =1.5V 0.8V 0.0V 1ns 2.0V Vth =1.5V 0.8V 1ns
7B9910-4
R2
TTL AC Test Load (CY7B9910)
VCC R1 CL R1=100 R2=100 CL = 50 pF (CL =30 pF for -5 and - 2devices) (Includes fixture and probe capacitance)
TTL Input Test Waveform (Cy7B9910)
VCC 80% Vth = VCC/2 20% 0.0V 3ns 80% Vth = VCC/2 20% 3ns
7B9910-6
R2
7B9910-5
CMOS AC Test Load (CY7B9920)
CMOS Input Test Waveform (CY7B9920)
3
CY7B9910 CY7B9920
Switching Characteristics Over the Operating Range[7]
CY7B9910-2[8] Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW[9, 10] FS = MID[9, 10] FS = HIGH[9, 10, 11] tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs) Device-to-Device Skew[14, 15] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation Output Rise Time[17, 18] Output Fall Time[17, 18] PLL Lock Time[19] Cycle-to-Cycle Output Jitter Peak to Peak RMS CY7B9910-5 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW[9, 10] FS = MID[9, 10] FS = HIGH[9, 10, 11] tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs)[13, 14] -0.5 -1.0 0.15 0.15 Peak[8] Device-to-Device Skew[8, 15] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[16] Output Rise PLL Lock Time[17, 18] Output Fall Time[17, 18] Time[19] RMS[8] Cycle-to-Cycle Output Jitter Peak to 0.0 0.0 1.0 1.0 Min. 15 25 40 5.0 5.0 0.25 0.5 1.0 +0.5 +1.0 1.5 1.5 0.5 200 25 -0.5 -1.0 0.5 0.5 0.0 0.0 2.0 2.0 Typ. Max. 30 50 80 Min. 15 25 40 5.0 5.0 0.25 0.5 1.0 +0.5 +1.0 3.0 3.0 0.5 200 25
[16] [13, 14]
CY7B9920-2[8] Min. 15 25 40 5.0 5.0 Typ. Max. 30 50 80[12] ns ns 0.1 -0.25 -0.65 0.5 0.5 0.0 0.0 2.0 2.0 0.25 0.75 +0.25 +0.65 2.5 2.5 0.5 200 25 CY7B9920-5 Typ. Max. 30 50 80[12] ns ns ns ns ns ns ns ns ms ps ps Unit MHz ns ns ns ns ns ns ms ps ps Unit MHz 30 50 80
Min. 15 25 40 5.0 5.0
Typ.
Max.
0.1 -0.25 -0.65 0.15 0.15 0.0 0.0 1.0 1.0
0.25 0.75 +0.25 +0.65 1.2 1.2 0.5 200 25
Notes: 7. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 10. The level to be set on FS is determined by the "normal" operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF and FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/X when the device is configured for a frequency multiplication by using external division in the feedback path of value X. 11. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V CC has reached 4.3V. 12. Except as noted, all CY7B9920-2 and -5 timing parameters are specified to 80-MHz with a 30-pF load. 13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50 to 2.06V (CY7B9910) or VCC/2 (CY7B9920). 14. tSKEW is defined as the skew between outputs. 15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, etc.). 16. tODCV is the deviation of the output from a 50% duty cycle. 17. Specified with outputs loaded with 30 pF for the CY7B99X0-2 and -5 devices and 50 pF for the CY7B99X0-7 devices. Devices are terminated through 50 to 2.06V (CY7B9910) or VCC/2 (CY7B9920). 18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920. 19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t PD is within specified limits.
4
CY7B9910 CY7B9920
Switching Characteristics Over the Operating Range[7] (continued)
CY7B9910-7 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW
[9, 10]
CY7B9920-7 Max. 30 50 80 Min. 15 25 40 5.0 5.0 Typ. Max. 30 50 80[12] ns ns 0.3 -0.7 -1.2 0.5 0.5 0.0 0.0 3.0 3.0 0.75 1.5 +0.7 +1.2 5.0 5.0 0.5 200 25 ns ns ns ns ns ns ms ps ps Unit MHz
Min. 15 25 40 5.0 5.0
[13, 14]
Typ.
FS = MID[9, 10] FS = HIGH tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR tJR REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs) Device-to-Device Skew
[8, 15] [9, 10, 11]
0.3 -0.7 -1.2 0.15 0.15 0.0 0.0 1.5 1.5
0.75 1.5 +0.7 +1.2 2.5 2.5 0.5 200 25
Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[16] Output Rise Output Fall PLL Lock Time[17, 18] Time[17, 18] Peak to Peak[8] RMS[8]
Time[19]
Cycle-to-Cycle Output Jitter
AC Timing Diagrams
tREF tRPWH REF tPD tODCV tRPWL
tODCV
FB
Q
tSKEW OTHER Q
tSKEW
tJR
7B9910-8
5
CY7B9910 CY7B9920
REF Z0 SYSTEM CLOCK FB REF FS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TEST Z0 Z0 Z0
LOAD
LOAD
LOAD
LOAD
7B9910-9
Figure 1. Zero-Skew and/or Zero-Delay Clock Driver
Operational Mode Descriptions
Figure 1 shows the device configured as a zero-skew clock buffer. In this mode the 7B9910/9920 can be used as the basis for a low-skew clock distribution tree. The outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any output and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive termi-
nated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design.
Figure 2 shows the CY7B9910/9920 connected in series to construct a zero-skew clock distribution tree between boards. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is not recommended that more than two clock buffers be connected in series.
REF Z0 FB SYSTEM CLOCK REF FS Z0
LOAD
LOAD Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Z0
LOAD
TEST Z0
FB REF FS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
LOAD
LOAD
TEST
7B9910-10
Figure 2. Board-to-Board Clock Distribution
6
CY7B9910 CY7B9920
Ordering Information
Accuracy (ps) 250 500 Ordering Code CY7B9910-2SC CY7B9920-2SC CY7B9910-5SC CY7B9910-5SI CY7B9920-5SC CY7B9920-5SI CY7B9910-7SC CY7B9910-7SI CY7B9920-7SC CY7B9920-7SI Package Name S13 S13 S13 S13 S13 S13 S13 S13 S13 S13 Package Type 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
750
Document #: 38-00437-B
Package Diagram
24-Lead (300-Mil) Molded SOIC S13
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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